IEEE1588v2 (PTP) EVB - Boundary, Slave and Master Clock
The IPC500 EVB - IEEE1588v2 Boundary and Master/Slave Clock enables equipment vendors and ASIC vendors to evaluate the IPC9000, IPC1710, IPC1603 chip on FPGA.
The IPC9000/IPC1710/IPC1603 is optimized for providing high quality frequency synchronization, phase alignment and accurate Time of Day (ToD) distribution over packet switched networks with the flexibility to operate either as PTP BC and/or Master and/or Slave.
With the IPC9000/IPC1710/IPC1603, the use of PTP is allowing leveraging the IP network for distributing the clock to the clients hence lowering the total network deployment and maintenance expenditures by reducing the number of GPS receivers to the minimum required.
The IPC500 incorporates IPClock’s state-of-the-art IPC9000/IPC1710/IPC1603 designed to meet packet switched networks inherent impairments with proved excellent clock synchronization performance.
Typical applications for IPC9000/IPC1710/IPC1603 include:
- Cellular IP backhauling
- Aerospace and defense
- Smart Grid
- Homeland security
- Passive Optical Networks (PON)
The IPC500 is an evaluation kit for the IPC9xxx, IPC17xx and IPC1603. The IPC9xxx, IPC17xx and IPC1603 utilize IPClock’s state-of-the-art technology for IEEE 1588 boundary, master and slave clocks optimized for providing high quality frequency synchronization and Time of Day (ToD) over packet networks. The IPC9xxx, IPC17xx and IPC1603 are implemented as chip on FPGA leveraging Xilinx® Spartan™ 6 FPGA, using 8MB of FLASH memory and 64MB of DDR II memory. The IPC500 has CLK IN, CLK OUT and PPS OUT clock interfaces via BNC connectors, 100/1000 Mbps Ethernet connection via RJ45, RS232 TOD interface via DB9 connector. The IPC500 can be managed by the user via the RS232 management port. The IPC500 has several LED indications: system power, device status (pass, alarm, fail), clock state (Free Run, Holdover, Trace, Lock). The IPC500 enable the user to explore the entire APIs set of IPClock’s devices by using simple CLI.
1PPS from GPS
1.544MHz, 2.048MHz, 10MHz
ToD Message Protocol: NMEA
100/1000 Base-T Ethernet
Management and Control
CLI based configuration and management via RS-232
Master / Slave
Unicast / Multicast
ITU-T G.8261 compliant
FR: Free Run