IPC5010
IEEE 1588 Slave Clock - IP Core
Overview
The IPC5010 utilizes IPClock’s state-of-the-art technology for IEEE 1588 v2 optimized for providing high quality frequency synchronization and Time of Day (ToD) over packet switched networks. Clock synchronization is required by many applications. For example, Universal Mobile Telecommunications System (UMTS) frequency-division duplexing (FDD) requires the synchronization of frequency while Long-Term Evolution (LTE) requires frequency synchronization, phase alignment and accurate time of day (ToD). The IPC5010 is an IP Core leveraging Xilinx® Zynq FPGA supporting 16MB of FLASH memory and 128MB of DDR3 memory. The IPC5010 is an application-agnostic, cost effective, reliable and standard compliant IEEE 1588 v2 designed for enabling applications requiring high synchronization level. The IPC5010 is designed for easy field upgrades to support future enhancements as well as future clock synchronization standards.
Description
The IPC5010 can be set to operate as IEEE 1588 Slave. IEEE 1588 protocol is a bidirectional protocol requiring all ports to transmit and receive IEEE 1588 packets. Each packet received its time-stamp by the Timestamp Generator and classified by the Classifier. In the case the packet is IEEE 1588 packet it is sent to the Pre-Processor along with its timestamp. The Pre-Processor is transferring the received general packets to the PTP Manager and Stack for further processing. In the case of IEEE 1588 event packet the Pre-Processor compensate for part of the packet network impairments and prepare the data for the Sync Processor. The Sync Processor is comprised of a suite of algorithms that processes the data and controls the 1PPS PLL, the programmable clock output of the Clock Generator, and the ToD. The ToD is communicating with the ToD UART utilizing the NMEA protocol for providing the ToD. The IEEE 1588 packets are transmitted by the Packet Generator which is controlled by the PTP Manager and Stack.
Features
- Standalone IEEE 1588 v2 standard Slave IP core for Xilinx Zynq
- Excellent synchronization performance over most extreme packet transport network conditions
- Slave ToD alignment error is better than ±1µsec on a managed 10-switch GbE network under ITU-T G.8261 conditions
- Slave frequency accuracy performance is better than 16ppb on a managed 10-switch GbE network under ITU-T G.8261 conditions
- Adaptive to network impairments
- Provides precision holdover
- Slave meets 3G, 4G-LTE frequency and ToD accuracy
- SGMII interface
- Hybrid IEEE 1588/SyncE support. Requires external SyncE PLL.
- Supports Unicast/Multicast
- Supports one step / two steps
- Low total cost of ownership
- Zero touch approach can make external CPU redundant
- Upgradeable by software
- Easy adding of enhancements and supporting emerging clock synchronization standards
- Operates with either TCXO or OCXO (20MHz)
- Interfacing generic PHY
- Modes of operation: Free run, Trace, Lock and Holdover